Whenever possible, you should use the general-purpose constraint letters
in asm
arguments, since they will convey meaning more readily to
people reading your code. Failing that, use the constraint letters
that usually have very similar meanings across architectures. The most
commonly used constraints are ‘m’ and ‘r’ (for memory and
general-purpose registers respectively; see Simple Constraints), and
‘I’, usually the letter indicating the most common
immediate-constant format.
Each architecture defines additional constraints. These constraints
are used by the compiler itself for instruction generation, as well as
for asm
statements; therefore, some of the constraints are not
particularly useful for asm
. Here is a summary of some of the
machine-dependent constraints available on some particular machines;
it includes both constraints that are useful for asm
and
constraints that aren't. The compiler source file mentioned in the
table heading for each architecture is the definitive reference for
the meanings of that architecture's constraints.
k
SP
)
w
I
ADD
instruction
J
SUB
instruction (once negated)
K
L
M
MOV
pseudo instruction. The MOV
may be assembled to one of several different
machine instructions depending on the value
N
MOV
pseudo instruction
S
Y
Z
Usa
Ush
Q
Ump
w
G
I
J
K
L
M
Q
asm
statements)
R
S
Uv
Uy
Uq
l
a
d
w
e
b
q
t
x
y
z
I
J
K
L
M
N
O
P
G
Q
U16
K
L
Cm1
Cl1
Cr1
Cal
i
, except that for position independent code,
no symbols / expressions needing relocations are allowed.
Csy
Rcs
Rsc
Rct
Rgs
Rra
Rcc
Sra
Cfm
UNSPEC_FP_MODE
.
b
t
p
I
J
K
L
M
N
G
a
f
q
x
y
Z
I
J
K
zdepi
instruction
L
M
N
ldil
instruction
O
P
and
operations in depi
and extru
instructions
S
U
G
A
lo_sum
data-linkage-table memory operand
Q
R
T
W
k
f
t
a
I
J
K
M
N
O
b
d
f
v
wa
When using any of the register constraints (wa
, wd
,
wf
, wg
, wh
, wi
, wj
, wk
,
wl
, wm
, ws
, wt
, wu
, wv
,
ww
, or wy
) that take VSX registers, you must use
%x<n>
in the template so that the correct register is used.
Otherwise the register number output in the assembly file will be
incorrect if an Altivec register is an operand of a VSX instruction
that expects VSX register numbering.
asm ("xvadddp %x0,%x1,%x2" : "=wa" (v1) : "wa" (v2), "wa" (v3));
is correct, but:
asm ("xvadddp %0,%1,%2" : "=wa" (v1) : "wa" (v2), "wa" (v3));
is not correct.
wd
wf
wg
wh
wi
wj
wk
wl
wm
wn
wr
ws
wt
wu
wv
ww
wx
wy
wz
wQ
lq
and stq
instructions.
h
q
c
l
x
y
z
I
J
SImode
constants)
K
L
M
N
O
P
G
H
m
m
does not allow addresses that update the base register.
If ‘<’ or ‘>’ constraint is also used, they are allowed and
therefore on PowerPC targets in that case it is only safe
to use ‘m<>’ in an asm
statement if that asm
statement
accesses the operand exactly once. The asm
statement must also
use ‘%U<opno>’ as a placeholder for the “update” flag in the
corresponding load or store instruction. For example:
asm ("st%U0 %1,%0" : "=m<>" (mem) : "r" (val));
is correct but:
asm ("st %1,%0" : "=m<>" (mem) : "r" (val));
is not.
es
Q
asm
statements)
Z
asm
statements)
R
a
asm
statements)
S
T
U
t
W
j
R
a
, b
, c
, d
,
si
, di
, bp
, sp
).
q
l
. In 32-bit mode, a
,
b
, c
, and d
; in 64-bit mode, any integer register.
Q
h
: a
, b
,
c
, and d
.
a
a
register.
b
b
register.
c
c
register.
d
d
register.
S
si
register.
D
di
register.
A
a
and d
registers. This class is used for instructions
that return double word results in the ax:dx
register pair. Single
word values will be allocated either in ax
or dx
.
For example on i386 the following implements rdtsc
:
unsigned long long rdtsc (void) { unsigned long long tick; __asm__ __volatile__("rdtsc":"=A"(tick)); return tick; }
This is not correct on x86_64 as it would allocate tick in either ax
or dx
. You have to use the following variant instead:
unsigned long long rdtsc (void) { unsigned int tickl, tickh; __asm__ __volatile__("rdtsc":"=a"(tickl),"=d"(tickh)); return ((unsigned long long)tickh << 32)|tickl; }
f
t
%st(0)
).
u
%st(1)
).
y
x
Yz
%xmm0
).
I
J
K
L
0xFF
or 0xFFFF
, for andsi as a zero-extending move.
M
lea
instruction).
N
in
and out
instructions).
G
C
e
Z
a
r0
to r3
for addl
instruction
b
c
d
e
f
m
G
I
J
K
L
M
N
O
P
dep
instruction
Q
R
shladd
instruction
S
a
ACC_REGS
(acc0
to acc7
).
b
EVEN_ACC_REGS
(acc0
to acc7
).
c
CC_REGS
(fcc0
to fcc3
and
icc0
to icc3
).
d
GPR_REGS
(gr0
to gr63
).
e
EVEN_REGS
(gr0
to gr63
).
Odd registers are excluded not in the class but through the use of a machine
mode larger than 4 bytes.
f
FPR_REGS
(fr0
to fr63
).
h
FEVEN_REGS
(fr0
to fr63
).
Odd registers are excluded not in the class but through the use of a machine
mode larger than 4 bytes.
l
LR_REG
(the lr
register).
q
QUAD_REGS
(gr2
to gr63
).
Register numbers not divisible by 4 are excluded not in the class but through
the use of a machine mode larger than 8 bytes.
t
ICC_REGS
(icc0
to icc3
).
u
FCC_REGS
(fcc0
to fcc3
).
v
ICR_REGS
(cc4
to cc7
).
w
FCR_REGS
(cc0
to cc3
).
x
QUAD_FPR_REGS
(fr0
to fr63
).
Register numbers not divisible by 4 are excluded not in the class but through
the use of a machine mode larger than 8 bytes.
z
SPR_REGS
(lcr
and lr
).
A
QUAD_ACC_REGS
(acc0
to acc7
).
B
ACCG_REGS
(accg0
to accg7
).
C
CR_REGS
(cc0
to cc7
).
G
I
J
L
M
N
O
P
a
d
z
q
nA
, then the register P0.
D
W
e
A
B
b
v
f
c
C
t
k
u
x
y
w
Ksh
Kuh
Ks7
Ku7
Ku5
Ks4
Ks3
Ku3
P
nPA
PB
M1
M2
J
L
H
Q
Rsp
Rfb
Rsb
Rcr
Rcl
R0w
R1w
R2w
R3w
R02
R13
Rdi
Rhl
R23
Raa
Raw
Ral
Rqi
Rad
Rsi
Rhi
Rhc
Rra
Rfl
Rmm
Rpi
Rpa
Is3
IS1
IS2
IU2
In4
In5
In6
IM2
Ilb
Ilw
Sd
Sa
Si
Ss
Sf
Ss
S1
a
b
c
d
em
ex
er
h
j
l
t
v
x
y
z
A
B
C
D
I
J
K
L
M
N
O
S
T
U
W
Y
Z
d
r0
to r31
).
z
rmsr
, $fcc1
to $fcc7
).
d
r
unless
generating MIPS16 code.
f
h
hi
register. This constraint is no longer supported.
l
lo
register. Use this register to store values that are
no bigger than a word.
x
hi
and lo
registers. Use this register
to store doubleword values.
c
$25
for -mabicalls.
v
$3
. Do not use this constraint in new code;
it is retained only for compatibility with glibc.
y
r
; retained for backwards compatibility.
z
I
J
K
L
lui
.
M
lui
, addiu
or ori
.
N
O
P
G
R
a
d
f
I
J
K
L
M
N
O
P
R
G
S
T
Q
U
W
Cs
Ci
C0
Cj
Cmvq
Capsw
Cmvz
Cmvs
Ap
Ac
A
B
W
I
N
a
d
f
G
I
J
K
L
M
N
O
Q
R
Int3
Int8
J
K
L
M
N
O
P
Qbi
Qsc
Wab
Wbc
BC
as a base register, with an optional offset.
Wca
AX
, BC
, DE
, or HL
for the address, for calls.
Wcv
Wd2
DE
as a base register, with an optional offset.
Wde
DE
as a base register, without any offset.
Wfr
Wh1
HL
as a base register, with an optional one-byte offset.
Whb
HL
as a base register, with B
or C
as the index register.
Whl
HL
as a base register, without any offset.
Ws1
SP
as a base register, with an optional one-byte offset.
Y
A
AX
register.
B
BC
register.
D
DE
register.
R
A
through L
registers.
S
SP
register.
T
HL
register.
Z08W
R8
register.
Z10W
R10
register.
Zint
R24
to R31
).
a
A
register.
b
B
register.
c
C
register.
d
D
register.
e
E
register.
h
H
register.
l
L
register.
v
w
PSW
register.
x
X
register.
Q
Symbol
Int08
Sint08
Sint16
Sint24
Uint04
f
e
c
d
b
h
C
A
D
I
J
K
sethi
instruction)
L
movcc
instructions (11-bit
signed immediate)
M
movrcc
instructions (10-bit
signed immediate)
N
SImode
O
G
H
P
Q
R
S
T
U
W
w
Y
a
c
d
iohl
instruction. const_int is treated as a 64 bit value.
f
fsmbi
.
A
B
C
D
iohl
instruction. const_int is treated as a 32 bit value.
I
J
K
M
stop
.
N
iohl
and fsmbi
.
O
P
R
S
T
U
W
Y
Z
iohl
instruction. const_int is sign extended to 128 bit.
a
c
d
f
I
J
K
L
(0..4095)
(−524288..524287)
M
N
0..9:
H,Q:
D,S,H:
0,F:
Q
R
S
T
U
W
Y
d
e
t
h
l
x
q
y
z
a
c
b
f
i
j
I
J
K
L
M
N
Z
a
b
c
d
e
t
y
z
I
J
K
L
M
N
O
P
Q
R
S
T
U
Z
a
b
A
B
C
Da
Db
Iu4
Iu5
In5
Is5
I5x
IuB
IsB
IsC
Jc
Js
Q
R
Z
R00
R01
R02
R03
R04
R05
R06
R07
R08
R09
R10
I
J
K
L
m
asm ("st_add %I0,%1,%i0" : "=m<>" (*mem) : "r" (val));
M
N
O
P
Q
S
T
U
W
Y
Z0
Z1
R00
R01
R02
R03
R04
R05
R06
R07
R08
R09
R10
I
J
K
L
m
asm ("swadd %I0,%1,%i0" : "=m<>" (mem) : "r" (val));
M
N
O
P
Q
T
U
W
Y
a
b
A
I
J
K
L