Whenever possible, you should use the general-purpose constraint letters
in asm arguments, since they will convey meaning more readily to
people reading your code. Failing that, use the constraint letters
that usually have very similar meanings across architectures. The most
commonly used constraints are ‘m’ and ‘r’ (for memory and
general-purpose registers respectively; see Simple Constraints), and
‘I’, usually the letter indicating the most common
immediate-constant format.
Each architecture defines additional constraints. These constraints
are used by the compiler itself for instruction generation, as well as
for asm statements; therefore, some of the constraints are not
particularly useful for asm. Here is a summary of some of the
machine-dependent constraints available on some particular machines;
it includes both constraints that are useful for asm and
constraints that aren't. The compiler source file mentioned in the
table heading for each architecture is the definitive reference for
the meanings of that architecture's constraints.
kSP)
wIADD
instruction
JSUB
instruction (once negated)
KLMMOV
pseudo instruction. The MOV may be assembled to one of several different
machine instructions depending on the value
NMOV
pseudo instruction
SYZUsaUshQUmpwGIJKLMQasm statements)
RSUvUyUqladwebqtxyzIJKLMNOPGQU16KLCm1Cl1Cr1Cali, except that for position independent code,
no symbols / expressions needing relocations are allowed.
CsyRcsRscRctRgsRraRccSraCfmUNSPEC_FP_MODE.
btpIJKLMNGafqxyZIJKzdepi instruction
LMNldil instruction
OPand operations in depi
and extru instructions
SUGAlo_sum data-linkage-table memory operand
QRTWkftaIJKMNObdfvwaWhen using any of the register constraints (wa, wd,
wf, wg, wh, wi, wj, wk,
wl, wm, ws, wt, wu, wv,
ww, or wy) that take VSX registers, you must use
%x<n> in the template so that the correct register is used.
Otherwise the register number output in the assembly file will be
incorrect if an Altivec register is an operand of a VSX instruction
that expects VSX register numbering.
asm ("xvadddp %x0,%x1,%x2" : "=wa" (v1) : "wa" (v2), "wa" (v3));
is correct, but:
asm ("xvadddp %0,%1,%2" : "=wa" (v1) : "wa" (v2), "wa" (v3));
is not correct.
wdwfwgwhwiwjwkwlwmwnwrwswtwuwvwwwxwywzwQlq and stq
instructions.
hqclxyzIJSImode constants)
KLMNOPGHmm does not allow addresses that update the base register.
If ‘<’ or ‘>’ constraint is also used, they are allowed and
therefore on PowerPC targets in that case it is only safe
to use ‘m<>’ in an asm statement if that asm statement
accesses the operand exactly once. The asm statement must also
use ‘%U<opno>’ as a placeholder for the “update” flag in the
corresponding load or store instruction. For example:
asm ("st%U0 %1,%0" : "=m<>" (mem) : "r" (val));
is correct but:
asm ("st %1,%0" : "=m<>" (mem) : "r" (val));
is not.
esQasm statements)
Zasm statements)
Raasm statements)
STUtWjRa, b, c, d,
si, di, bp, sp).
ql. In 32-bit mode, a,
b, c, and d; in 64-bit mode, any integer register.
Qh: a, b,
c, and d.
aa register.
bb register.
cc register.
dd register.
Ssi register.
Ddi register.
Aa and d registers. This class is used for instructions
that return double word results in the ax:dx register pair. Single
word values will be allocated either in ax or dx.
For example on i386 the following implements rdtsc:
unsigned long long rdtsc (void)
{
unsigned long long tick;
__asm__ __volatile__("rdtsc":"=A"(tick));
return tick;
}
This is not correct on x86_64 as it would allocate tick in either ax
or dx. You have to use the following variant instead:
unsigned long long rdtsc (void)
{
unsigned int tickl, tickh;
__asm__ __volatile__("rdtsc":"=a"(tickl),"=d"(tickh));
return ((unsigned long long)tickh << 32)|tickl;
}
ft%st(0)).
u%st(1)).
yxYz%xmm0).
IJKL0xFF or 0xFFFF, for andsi as a zero-extending move.
Mlea instruction).
Nin and out
instructions).
GCeZar0 to r3 for addl instruction
bcdefmGIJKLMNOPdep instruction
QRshladd instruction
SaACC_REGS (acc0 to acc7).
bEVEN_ACC_REGS (acc0 to acc7).
cCC_REGS (fcc0 to fcc3 and
icc0 to icc3).
dGPR_REGS (gr0 to gr63).
eEVEN_REGS (gr0 to gr63).
Odd registers are excluded not in the class but through the use of a machine
mode larger than 4 bytes.
fFPR_REGS (fr0 to fr63).
hFEVEN_REGS (fr0 to fr63).
Odd registers are excluded not in the class but through the use of a machine
mode larger than 4 bytes.
lLR_REG (the lr register).
qQUAD_REGS (gr2 to gr63).
Register numbers not divisible by 4 are excluded not in the class but through
the use of a machine mode larger than 8 bytes.
tICC_REGS (icc0 to icc3).
uFCC_REGS (fcc0 to fcc3).
vICR_REGS (cc4 to cc7).
wFCR_REGS (cc0 to cc3).
xQUAD_FPR_REGS (fr0 to fr63).
Register numbers not divisible by 4 are excluded not in the class but through
the use of a machine mode larger than 8 bytes.
zSPR_REGS (lcr and lr).
AQUAD_ACC_REGS (acc0 to acc7).
BACCG_REGS (accg0 to accg7).
CCR_REGS (cc0 to cc7).
GIJLMNOPadzqnA, then the register P0.
DWeABbvfcCtkuxywKshKuhKs7Ku7Ku5Ks4Ks3Ku3PnPAPBM1M2JLH
QRspRfbRsbRcrRclR0wR1wR2wR3wR02R13RdiRhlR23RaaRawRalRqiRadRsiRhiRhcRraRflRmmRpiRpaIs3IS1IS2IU2In4In5In6IM2IlbIlwSdSaSiSsSfSsS1abcdemexerhjltvxyzABCDIJKLMNOSTUWYZdr0 to r31).
zrmsr, $fcc1 to $fcc7).
dr unless
generating MIPS16 code.
fhhi register. This constraint is no longer supported.
llo register. Use this register to store values that are
no bigger than a word.
xhi and lo registers. Use this register
to store doubleword values.
c$25 for -mabicalls.
v$3. Do not use this constraint in new code;
it is retained only for compatibility with glibc.
yr; retained for backwards compatibility.
zIJKLlui.
Mlui, addiu
or ori.
NOPGRadfIJKLMNOPRGSTQUWCsCiC0CjCmvqCapswCmvzCmvsApAcABWINadfGIJKLMNOQRInt3Int8JKLMNOPQbiQscWabWbcBC as a base register, with an optional offset.
WcaAX, BC, DE, or HL for the address, for calls.
WcvWd2DE as a base register, with an optional offset.
WdeDE as a base register, without any offset.
WfrWh1HL as a base register, with an optional one-byte offset.
WhbHL as a base register, with B or C as the index register.
WhlHL as a base register, without any offset.
Ws1SP as a base register, with an optional one-byte offset.
YAAX register.
BBC register.
DDE register.
RA through L registers.
SSP register.
THL register.
Z08WR8 register.
Z10WR10 register.
ZintR24 to R31).
aA register.
bB register.
cC register.
dD register.
eE register.
hH register.
lL register.
vwPSW register.
xX register.
QSymbolInt08Sint08Sint16Sint24Uint04fecdbhCADIJKsethi instruction)
Lmovcc instructions (11-bit
signed immediate)
Mmovrcc instructions (10-bit
signed immediate)
NSImode
OGHPQRSTUWwYacdiohl instruction. const_int is treated as a 64 bit value.
ffsmbi.
ABCDiohl instruction. const_int is treated as a 32 bit value.
IJKMstop.
Niohl and fsmbi.
OPRSTUWYZiohl instruction. const_int is sign extended to 128 bit.
acdfIJKL(0..4095)(−524288..524287)MN0..9:H,Q:D,S,H:0,F:QRSTUWYdethlxqyzacbfijIJKLMNZabcdetyzIJKLMNOPQRSTUZabABCDaDbIu4Iu5In5Is5I5xIuBIsBIsCJcJsQRZR00R01R02R03R04R05R06R07R08R09R10IJKLm asm ("st_add %I0,%1,%i0" : "=m<>" (*mem) : "r" (val));
MNOPQSTUWYZ0Z1R00R01R02R03R04R05R06R07R08R09R10IJKLm asm ("swadd %I0,%1,%i0" : "=m<>" (mem) : "r" (val));
MNOPQTUWYabAIJKL