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6.56.3 ARM NEON Intrinsics

These built-in intrinsics for the ARM Advanced SIMD extension are available when the -mfpu=neon switch is used:

6.56.3.1 Addition
6.56.3.2 Multiplication
6.56.3.3 Multiply-accumulate
6.56.3.4 Multiply-subtract
6.56.3.5 Fused-multiply-accumulate
6.56.3.6 Fused-multiply-subtract
6.56.3.7 Round to integral (to nearest, ties to even)
6.56.3.8 Round to integral (to nearest, ties away from zero)
6.56.3.9 Round to integral (towards +Inf)
6.56.3.10 Round to integral (towards -Inf)
6.56.3.11 Round to integral (towards 0)
6.56.3.12 Subtraction
6.56.3.13 Comparison (equal-to)
6.56.3.14 Comparison (greater-than-or-equal-to)
6.56.3.15 Comparison (less-than-or-equal-to)
6.56.3.16 Comparison (greater-than)
6.56.3.17 Comparison (less-than)
6.56.3.18 Comparison (absolute greater-than-or-equal-to)
6.56.3.19 Comparison (absolute less-than-or-equal-to)
6.56.3.20 Comparison (absolute greater-than)
6.56.3.21 Comparison (absolute less-than)
6.56.3.22 Test bits
6.56.3.23 Absolute difference
6.56.3.24 Absolute difference and accumulate
6.56.3.25 Maximum
6.56.3.26 Minimum
6.56.3.27 Pairwise add
6.56.3.28 Pairwise add, single_opcode widen and accumulate
6.56.3.29 Folding maximum
6.56.3.30 Folding minimum
6.56.3.31 Reciprocal step
6.56.3.32 Vector shift left
6.56.3.33 Vector shift left by constant
6.56.3.34 Vector shift right by constant
6.56.3.35 Vector shift right by constant and accumulate
6.56.3.36 Vector shift right and insert
6.56.3.37 Vector shift left and insert
6.56.3.38 Absolute value
6.56.3.39 Negation
6.56.3.40 Bitwise not
6.56.3.41 Count leading sign bits
6.56.3.42 Count leading zeros
6.56.3.43 Count number of set bits
6.56.3.44 Reciprocal estimate
6.56.3.45 Reciprocal square-root estimate
6.56.3.46 Get lanes from a vector
6.56.3.47 Set lanes in a vector
6.56.3.48 Create vector from literal bit pattern
6.56.3.49 Set all lanes to the same value
6.56.3.50 Combining vectors
6.56.3.51 Splitting vectors
6.56.3.52 Conversions
6.56.3.53 Move, single_opcode narrowing
6.56.3.54 Move, single_opcode long
6.56.3.55 Table lookup
6.56.3.56 Extended table lookup
6.56.3.57 Multiply, lane
6.56.3.58 Long multiply, lane
6.56.3.59 Saturating doubling long multiply, lane
6.56.3.60 Saturating doubling multiply high, lane
6.56.3.61 Multiply-accumulate, lane
6.56.3.62 Multiply-subtract, lane
6.56.3.63 Vector multiply by scalar
6.56.3.64 Vector long multiply by scalar
6.56.3.65 Vector saturating doubling long multiply by scalar
6.56.3.66 Vector saturating doubling multiply high by scalar
6.56.3.67 Vector multiply-accumulate by scalar
6.56.3.68 Vector multiply-subtract by scalar
6.56.3.69 Vector extract
6.56.3.70 Reverse elements
6.56.3.71 Bit selection
6.56.3.72 Transpose elements
6.56.3.73 Zip elements
6.56.3.74 Unzip elements
6.56.3.75 Element/structure loads, VLD1 variants
6.56.3.76 Element/structure stores, VST1 variants
6.56.3.77 Element/structure loads, VLD2 variants
6.56.3.78 Element/structure stores, VST2 variants
6.56.3.79 Element/structure loads, VLD3 variants
6.56.3.80 Element/structure stores, VST3 variants
6.56.3.81 Element/structure loads, VLD4 variants
6.56.3.82 Element/structure stores, VST4 variants
6.56.3.83 Logical operations (AND)
6.56.3.84 Logical operations (OR)
6.56.3.85 Logical operations (exclusive OR)
6.56.3.86 Logical operations (AND-NOT)
6.56.3.87 Logical operations (OR-NOT)
6.56.3.88 Reinterpret casts