Next: , Up: Submodel Options

3.17.1 AArch64 Options

These options are defined for AArch64 implementations:

-mbig-endian
Generate big-endian code. This is the default when GCC is configured for an ‘aarch64_be-*-*’ target.
-mgeneral-regs-only
Generate code which uses only the general registers.
-mlittle-endian
Generate little-endian code. This is the default when GCC is configured for an ‘aarch64-*-*’ but not an ‘aarch64_be-*-*’ target.
-mcmodel=tiny
Generate code for the tiny code model. The program and its statically defined symbols must be within 1GB of each other. Pointers are 64 bits. Programs can be statically or dynamically linked. This model is not fully implemented and mostly treated as ‘small’.
-mcmodel=small
Generate code for the small code model. The program and its statically defined symbols must be within 4GB of each other. Pointers are 64 bits. Programs can be statically or dynamically linked. This is the default code model.
-mcmodel=large
Generate code for the large code model. This makes no assumptions about addresses and sizes of sections. Pointers are 64 bits. Programs can be statically linked only.
-mstrict-align
Do not assume that unaligned memory references will be handled by the system.
-momit-leaf-frame-pointer
-mno-omit-leaf-frame-pointer
Omit or keep the frame pointer in leaf functions. The former behaviour is the default.
-mtls-dialect=desc
Use TLS descriptors as the thread-local storage mechanism for dynamic accesses of TLS variables. This is the default.
-mtls-dialect=traditional
Use traditional TLS as the thread-local storage mechanism for dynamic accesses of TLS variables.
-mfix-cortex-a53-835769
-mno-fix-cortex-a53-835769
Enable or disable the workaround for the ARM Cortex-A53 erratum number 835769. This will involve inserting a NOP instruction between memory instructions and 64-bit integer multiply-accumulate instructions.
-march=name
Specify the name of the target architecture, optionally suffixed by one or more feature modifiers. This option has the form -march=arch{+[no]feature}*, where the only value for arch is ‘armv8-a’. The possible values for feature are documented in the sub-section below.

Where conflicting feature modifiers are specified, the right-most feature is used.

GCC uses this name to determine what kind of instructions it can emit when generating assembly code. This option can be used in conjunction with or instead of the -mcpu= option.

-mcpu=name
Specify the name of the target processor, optionally suffixed by one or more feature modifiers. This option has the form -mcpu=cpu{+[no]feature}*, where the possible values for cpu are ‘generic’, ‘large’. The possible values for feature are documented in the sub-section below.

Where conflicting feature modifiers are specified, the right-most feature is used.

GCC uses this name to determine what kind of instructions it can emit when generating assembly code.

-mtune=name
Specify the name of the processor to tune the performance for. The code will be tuned as if the target processor were of the type specified in this option, but still using instructions compatible with the target processor specified by a -mcpu= option. This option cannot be suffixed by feature modifiers.
3.17.1.1 -march and -mcpu feature modifiers

Feature modifiers used with -march and -mcpu can be one the following:

‘crypto’
Enable Crypto extension. This implies Advanced SIMD is enabled.
‘fp’
Enable floating-point instructions.
‘simd’
Enable Advanced SIMD instructions. This implies floating-point instructions are enabled. This is the default for all current possible values for options -march and -mcpu=.